"Mr. Sutherland's expert knowledge of SystemVerilog provides insight not possible from other courses." |
 |
Workshop Descriptions
Click here to download the full syllabus for all Sutherland HDL workshops (a PDF document).
Comprehensive Verilog and SystemVerilog for Design and Synthesis
- 4-day comprehensive training on the latest generation of the Verilog language
- Includes the synthesizable SystemVerilog extensions to Verilog
- Audience: This workshop is for digital engineers who will be designing ASICs, FPGAs or systems with Verilog.
SystemVerilog Synthesis for Verilog Design Engineers
- 2-day in-depth training on the synthesizable subset of SystemVerilog
- Covers how to properly use packages, new data types, new programming statements, and interfaces
- Audience: Experienced Verilog design engineers who want to benefit from the powerful SystemVerilog synthesizable constructs
Accelerated Verilog Primer
- 2-day fast-paced workshop on modeling hardware with Verilog and SystemVerilog
- Thorough introduction of the Verilog language, with a focus on reading and maintaining models
- Audience: This course is intended for verification engineers and engineering managers who need to understand Verilog models, but who do not need to model and synthesize complex designs
SystemVerilog Testbench for Verilog Verification Engineers
- 3-day advanced-level workshop on using SystemVerilog for verification
- Presents the concepts of object-oriented verification
- Applies classes, semaphores, mailboxes, dynamic arrays, constrained random testing, and coverage
- Emphasizes creating advanced-level testbenches and verification programs
- Audience: This workshop is for design and verification engineers who are already familiar with Verilog
SystemVerilog Testbench for non-Verilog Verification Engineers
- 4-day advanced-level workshop on using SystemVerilog for verification
- Combines the Acclerated Verilog Primer and SystemVerilog Testbench workshops
- Presents the modeling constructs in Verilog and SystemVerilog
- Emphasizes creating advanced-level testbenches and verification programs
- Audience: This workshop is for verification engineers who have prior experience in other HDLs, such as VHDL, VERA, e, or SystemC
Advanced SystemVerilog Assertions for Design and Verification Engineers
- 2-day advanced-level workshop writing SystemVerilog Assertions
- Students learn to write complex assertion sequences for a variety of complex digital logic circuits
- Audience: Both design engineers and verification engineers will find this course beneficial
Advanced SystemVerilog Open Verification Methodology (OVM)
- 3-day workshop on developing testbenches using the OVM public standard
- Emphasis on proper verification methodology
- Audience: This workshop is for verification engineers who are already familiar with the SystemVerilog testbench constructs
- Developed and presented by Willamette HDL; offered through Sutherland HDL
Practical Application of the Verification Methodology Manual Using SystemVerilog
- 1-day workshop on the Verification Methodology Manual (VMM)
- Provides a thorough overview of writing advanced VMM testbenches
- Audience: This workshop is for verification engineers who are already familiar with the SystemVerilog testbench constructs
- Developed and presented by VHDLCohen; offered through Sutherland HDL
Verilog-2005 PLI 2.0 (VPI) with SystemVerilog DPI
- 3-day workshop on using the VPI portion of the Verilog Programming Interface
- Emphasis on writing portable PLI programs that work with all Verilog simulators
- Using the new SystemVerilog Direct Programming Interface (DPI)
- Audience: This workshop is for Verilog design and verification engineers who wish to customize Verilog simulators
Comprehensive VHDL for Simulation and Verification
- 4-day workshop covering the aspects of the IEEE 1076 VHDL standard IEEE 1164 Standard Logic
- Focus is on using VHDL for top-down design with synthesis and simulation
- Audience: This workshop is for digital engineers who will be designing ASICs, FPGAs or systems with VHDL
- Developed and presented by LCDM Engineering; offered through Sutherland HDL
|
|
|
